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i want to implement ggml_compute_forward in FPGA, just use the same interface params and node。the params and node control information would be generated in CPU and real calculation in FPGA。i dont really understand the node data structure , because it contains another two ggml_tensor src and view_src。i want to write all params and non-ggml-tensor information to a region that can be accessed by fpga and cpu, how would the ggml-tensor in node be accessed ? who can help to expain the data layout of node data structure or provide some materials?
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i want to implement ggml_compute_forward in FPGA, just use the same interface params and node。the params and node control information would be generated in CPU and real calculation in FPGA。i dont really understand the node data structure , because it contains another two ggml_tensor src and view_src。i want to write all params and non-ggml-tensor information to a region that can be accessed by fpga and cpu, how would the ggml-tensor in node be accessed ? who can help to expain the data layout of node data structure or provide some materials?
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