From 1cfc2cf8e2e5f4f3e702bb6d96e3b1cf46aaeaca Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 14 Feb 2025 09:20:15 +0100
Subject: [PATCH] phy/rmii: Cleanup LiteEthPHYRMIISpeedDetect. - Avoid CSR that
 was useful for debug. - Make signals local. - Add crs_dv/crs_last/rx_data
 argument to LiteEthPHYRMIISpeedDetect. - Avoid exposing count threshold since
 internal.

---
 liteeth/phy/rmii.py | 71 ++++++++++++++++++++-------------------------
 1 file changed, 32 insertions(+), 39 deletions(-)

diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py
index 1b003be..4c8d11c 100644
--- a/liteeth/phy/rmii.py
+++ b/liteeth/phy/rmii.py
@@ -41,47 +41,44 @@ def __init__(self, speed):
 # LiteEth PHY RMII Speed Detect --------------------------------------------------------------------
 
 class LiteEthPHYRMIISpeedDetect(LiteXModule):
-    def __init__(self, speed_counter_threshold=20):
-        self.crs_dv     = Signal()
-        self.rx_data    = Signal()
-        self.fsm_rst    = Signal()
-        self.speed      = Signal() # 0: 10Mbps, 1: 100Mbps.
-
-        self._speed_cnt = CSRStatus(10, description="CRS_DV to RX_DATA0 Delay.")
+    def __init__(self, csr_dv, crs_last, rx_data):
+        self.speed = Signal() # 0: 10Mbps, 1: 100Mbps.
 
         # # #
 
-        self.crs_dv_d   = Signal()
-        self.rx_data0_d = Signal()
-        self.cnt        = Signal(10) # FIXME: too big
-
-        self.comb += self._speed_cnt.status.eq(self.cnt)
+        # Signals.
+        crs_dv_d  = Signal()
+        rx_data_d = Signal()
+        count     = Signal(8)
 
-        self.fsm = fsm = FSM(reset_state="IDLE")
+        # FSM.
+        self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
+        self.comb += fsm.reset.eq(crs_last)
         fsm.act("IDLE",
-            If(self.crs_dv,
-                NextValue(self.cnt, 0),
+            If(crs_dv,
+                NextValue(count, 0),
                 NextState("DETECT")
             )
         )
 
         fsm.act("DETECT",
-            NextValue(self.cnt, self.cnt + 1),
-            If(~self.rx_data0_d & self.rx_data,
-                If((self.cnt < speed_counter_threshold),
+            NextValue(count, count + 1),
+            If(~rx_data_d & rx_data,
+                If(count < 20,
                     NextValue(self.speed, 1), # 100Mbps
                 ).Else(
                     NextValue(self.speed, 0), # 10Mbps
                 ),
-                NextState("HOLD_SPEED"),
+                NextState("HOLD"),
             ),
-            If(~self.crs_dv,  # If packet ends too soon
-                NextState("HOLD_SPEED")
+            # If packet ends too soon, hold speed.
+            If(~crs_dv,
+                NextState("HOLD")
             )
         )
 
-        fsm.act("HOLD_SPEED",
-            If(self.fsm_rst, NextState("IDLE"))
+        fsm.act("HOLD",
+            NextState("HOLD")
         )
 
 # LiteEth PHY RMII TX ------------------------------------------------------------------------------
@@ -172,6 +169,15 @@ def __init__(self, pads, clk_signal, speed_counter_threshold=20):
             If(crs_last,  crs_run.eq(0)),
         ]
 
+        # Speed Detection.
+        # ----------------
+        self.speed_detect = LiteEthPHYRMIISpeedDetect(
+            crs_dv   = csr_dv_i,
+            crs_last = crs_last,
+            rx_data  = rx_data_i,
+        )
+        self.comb += self.speed.eq(self.speed_detect.speed)
+
         # Datapath: Input -> Delay -> Converter -> Source.
         # ------------------------------------------------
         self.comb += [
@@ -186,16 +192,6 @@ def __init__(self, pads, clk_signal, speed_counter_threshold=20):
             converter.source.connect(source),
         ]
 
-        # Speed Detection.
-        # ----------------
-        self.speed_detect = LiteEthPHYRMIISpeedDetect(speed_counter_threshold)
-        self.comb += [
-            self.speed_detect.crs_dv.eq(crs_dv_i),
-            self.speed_detect.rx_data.eq(rx_data_i),
-            self.speed_detect.fsm_rst.eq(crs_last),
-            self.speed.eq(self.speed_detect.speed),
-        ]
-
 # LiteEth PHY RMII CRG -----------------------------------------------------------------------------
 
 class LiteEthPHYRMIICRG(LiteXModule):
@@ -251,7 +247,7 @@ class LiteEthPHYRMII(LiteXModule):
     dw          = 8
     tx_clk_freq = 50e6
     rx_clk_freq = 50e6
-    def __init__(self, clock_pads, pads, refclk_cd="eth", speed_counter_threshold=20,
+    def __init__(self, clock_pads, pads, refclk_cd="eth",
         with_hw_init_reset     = True,
         with_refclk_ddr_output = True):
 
@@ -265,11 +261,8 @@ def __init__(self, clock_pads, pads, refclk_cd="eth", speed_counter_threshold=20
         # TX/RX.
         # ------
         self.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads, self.crg.clk_signal))
-        self.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads,
-            clk_signal              = self.crg.clk_signal,
-            speed_counter_threshold = speed_counter_threshold
-        ))
-        self.comb             += self.tx.speed.eq(self.rx.speed)
+        self.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads, self.crg.clk_signal))
+        self.comb += self.tx.speed.eq(self.rx.speed)
         self.sink, self.source = self.tx.sink, self.rx.source
 
         # MDIO.