From ccca20021acbe2355dba76e0f62767b825ee0450 Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Thu, 16 Jan 2025 10:04:26 +0100 Subject: [PATCH 1/2] docs: add NDK performance report --- core/doc/img/perf_report_dma_calypte.svg | 2515 +++++++++++++++ core/doc/img/perf_report_dma_calypte_pps.svg | 2615 +++++++++++++++ core/doc/img/perf_report_dma_medusa.svg | 3049 ++++++++++++++++++ core/doc/img/perf_report_dma_medusa_pps.svg | 3049 ++++++++++++++++++ core/doc/img/perf_report_ethernet.svg | 2570 +++++++++++++++ core/doc/performance.rst | 64 + doc/source/index.rst | 1 + 7 files changed, 13863 insertions(+) create mode 100644 core/doc/img/perf_report_dma_calypte.svg create mode 100644 core/doc/img/perf_report_dma_calypte_pps.svg create mode 100644 core/doc/img/perf_report_dma_medusa.svg create mode 100644 core/doc/img/perf_report_dma_medusa_pps.svg create mode 100644 core/doc/img/perf_report_ethernet.svg create mode 100644 core/doc/performance.rst diff --git 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b/core/doc/performance.rst @@ -0,0 +1,64 @@ +.. _ndk_performance: + +Performance report +================== + +The aim of this chapter is to show selected realistic performance parameters that can be achieved with the NDK framework. +We focus on the speed of the Ethernet interface for communication over the network and +on the speed of the DMA IPs (see the :ref:`DMA module docs `) for packet data transfers between the FPGA and the host server. + +.. NOTE:: + The following performance values are only indicative. + The performance can be significantly influenced by, for example, + the used PC/server (especially the speed of the CPU, RAM, and PCIe interface) + and also the selected card or FPGA chip. + +Ethernet Interface +****************** + +In this test, we measure L2 throughput on the RX Ethernet interface. +A generator implemented in the FPGA is used as the source of Ethernet frames. +It generates frames of the selected size at full speed and +sends them to the TX Ethernet interface with an enabled PMA loopback to be passed back through the RX Ethernet interface. + +.. image:: img/perf_report_ethernet.svg + :align: center + :width: 100 % + +DMA Medusa IP +************* + +DMA Medusa is a closed-source DMA IP optimized for high-speed data transfers (up to 400 Gbps) and supports multiple PCIe endpoints. +The test uses multiple DMA channels and round-robin packet distribution. +The throughput test is performed in three phases: + +* F2H - we measure the throughput of packet data transfers from the FPGA to the RAM of the host server; packets are generated in the FPGA. +* H2F - we measure the throughput of packet data transfers from the RAM of the host server to the FPGA; packets are generated in SW. +* H2F2H - we measure the throughput of both directions simultaneously; packets are generated in SW, received in the FPGA, passed through a loopback, and transmitted back to SW. + +.. image:: img/perf_report_dma_medusa.svg + :align: center + :width: 100 % + +.. image:: img/perf_report_dma_medusa_pps.svg + :align: center + :width: 100 % + +DMA Calypte IP +************** + +DMA Calypte is an open-source DMA IP optimized for low-latency data transfers. +The test uses multiple DMA channels and round-robin packet distribution. +The throughput test is performed in three phases: + +* F2H - we measure the throughput of packet data transfers from the FPGA to the RAM of the host server; packets are generated in the FPGA. +* H2F - we measure the throughput of packet data transfers from the RAM of the host server to the FPGA; packets are generated in SW. +* H2F2H - we measure the throughput of both directions simultaneously; packets are generated in SW, received in the FPGA, passed through a loopback, and transmitted back to SW. + +.. image:: img/perf_report_dma_calypte.svg + :align: center + :width: 100 % + +.. image:: img/perf_report_dma_calypte_pps.svg + :align: center + :width: 100 % diff --git a/doc/source/index.rst b/doc/source/index.rst index 95cf2d390..2cf2038c7 100644 --- a/doc/source/index.rst +++ b/doc/source/index.rst @@ -14,6 +14,7 @@ Overview ndk_core/doc/how_to_start ndk_core/doc/terminology ndk_core/doc/readme + ndk_core/doc/performance ndk_core/doc/configuration ndk_core/doc/testing ndk_build/readme From 42a2c328bf89c1923d08ff90950a0263d39c8f7c Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Fri, 17 Jan 2025 09:42:37 +0100 Subject: [PATCH 2/2] docs: update the DMA module docs --- core/doc/dma.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/doc/dma.rst b/core/doc/dma.rst index 764a9e450..11b0b049f 100644 --- a/core/doc/dma.rst +++ b/core/doc/dma.rst @@ -7,7 +7,7 @@ The DMA module The DMA module is a wrapper containing the DMA controller (DMA IP), auxiliary, and debug logic. The connection of the DMA module is shown in the block diagram below. The DMA module is parametric and handles different numbers of DMA streams. The number of DMA streams corresponds to the number of instantiated DMA controllers. The currently supported DMA controllers in NDK are: - **DMA Medusa IP** -- Closed-source DMA controller optimized for high throughput (up to 400 Gbps) and support for multiple PCIe endpoints. See the :ref:`DMA Medusa IP documentation ` for a detailed description. -- **DMA Calypte IP** -- Open-source DMA controller optimized for low latency communication and supports only one PCIe endpoint. DMA Calypte IP is still under development and not yet ready for use! See the :ref:`DMA Calypte IP documentation ` for a detailed description. +- **DMA Calypte IP** -- Open-source DMA controller optimized for low latency communication and supports only one PCIe endpoint. See the :ref:`DMA Calypte IP documentation ` for a detailed description. .. note::