diff --git a/comp/uvm/logic_vector_array_avst/sequence.sv b/comp/uvm/logic_vector_array_avst/sequence.sv index a37e4feff..c9a9c6ec4 100644 --- a/comp/uvm/logic_vector_array_avst/sequence.sv +++ b/comp/uvm/logic_vector_array_avst/sequence.sv @@ -18,7 +18,6 @@ class sequence_simple_rx_base #(int unsigned REGIONS, int unsigned REGION_SIZE, uvm_avst::sequence_item #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH) gen; typedef enum {state_last, state_next, state_reset, state_overflow, state_latency} state_t; - state_t state = state_next; sequencer_rx #(ITEM_WIDTH, META_WIDTH) hl_sqr; @@ -88,42 +87,45 @@ class sequence_simple_rx_base #(int unsigned REGIONS, int unsigned REGION_SIZE, gen.randomize(); gen.valid = '0; state_packet = state_packet_space_new; - state = state_next; get_response(rsp); + + simple_reg.latency_cnt = READY_LATENCY; end else begin // get next item - if (state == state_next) begin - create_sequence_item(); - end + create_sequence_item(); //GET response get_response(rsp); // Solution of Ready Latency - if (rsp.ready == 0 && rsp.valid != 0) begin + if (rsp.ready == 0 && req.valid != 0) begin simple_reg.latency_cnt++; if (simple_reg.latency_cnt >= READY_LATENCY) begin do begin - send_empty_frame(); + if (READY_LATENCY == 0) begin + start_item(req); + finish_item(req); + end else begin + send_empty_frame(); + end get_response(rsp); end while(rsp.ready != 1); - assert(std::randomize(simple_reg.latency_cnt) with {simple_reg.latency_cnt inside {[0 : (READY_LATENCY - 1)]}; }) else `uvm_fatal(this.get_full_name(), "\n\tCannot randomize latency"); - for (int unsigned it = 0; it < simple_reg.latency_cnt; it++) begin - send_empty_frame(); - get_response(rsp); - end + //assert(std::randomize(simple_reg.latency_cnt) with {simple_reg.latency_cnt inside {[0 : (READY_LATENCY - 1)]}; }) else `uvm_fatal(this.get_full_name(), "\n\tCannot randomize latency"); + //for (int unsigned it = 0; it < simple_reg.latency_cnt; it++) begin + // send_empty_frame(); + // get_response(rsp); + //end simple_reg.latency_cnt = 0; end - end else if(rsp.ready == 1) + end else if(rsp.ready == 1) begin simple_reg.latency_cnt = 0; + end end //SEND FRAME start_item(req); - if (state != state_last) begin - req.copy(gen); - end + req.copy(gen); finish_item(req); endtask @@ -151,7 +153,7 @@ class sequence_simple_rx_base #(int unsigned REGIONS, int unsigned REGION_SIZE, req.valid = '0; gen.valid = '0; - while (hl_transactions > 0 || data != null || state == state_last || |gen.valid) begin + while (hl_transactions > 0 || data != null || |gen.valid) begin send_frame(); end //Get last response diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/Modules.tcl b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/Modules.tcl index dffc9a555..94001e43b 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/Modules.tcl +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/Modules.tcl @@ -23,4 +23,5 @@ lappend MOD "$ENTITY_BASE/tbench/env/pkg.sv" lappend MOD "$ENTITY_BASE/tbench/tests/pkg.sv" lappend MOD "$ENTITY_BASE/tbench/dut.sv" +lappend MOD "$ENTITY_BASE/tbench/property.sv" lappend MOD "$ENTITY_BASE/tbench/testbench.sv" diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/dut.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/dut.sv index 42224f1e6..3fcf724bd 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/dut.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/dut.sv @@ -42,16 +42,23 @@ module DUT ( logic [CQ_MFB_REGIONS*128-1 : 0] down_hdr ; logic [CQ_MFB_REGIONS*32-1 : 0] down_prefix ; logic [CQ_MFB_REGIONS*3-1 : 0] down_bar_range; + logic [CQ_MFB_REGIONS-1:0] down_valid; logic [CC_MFB_REGIONS*128-1 : 0] up_hdr; logic [CC_MFB_REGIONS*32-1 : 0] up_prefix; logic [CC_MFB_REGIONS-1 : 0] up_error; + logic down_ready; + + assign avst_down.READY = down_ready; generate for (genvar r = 0; r < CQ_MFB_REGIONS; r++) begin assign down_bar_range [(r+1)*BAR_RANGE_WIDTH-1 : r*BAR_RANGE_WIDTH] = avst_down.META[(r+1)*(AVST_DOWN_META_W)-1 : (r+1)*AVST_DOWN_META_W - BAR_RANGE_WIDTH]; assign down_prefix [(r+1)*PREFIX_WIDTH-1 : r*PREFIX_WIDTH] = avst_down.META[(r+1)*AVST_DOWN_META_W - BAR_RANGE_WIDTH-1 : (r+1)*AVST_DOWN_META_W - PREFIX_WIDTH - BAR_RANGE_WIDTH]; assign down_hdr [(r+1)*HDR_WIDTH-1 : r*HDR_WIDTH] = avst_down.META[(r+1)*AVST_DOWN_META_W - PREFIX_WIDTH - BAR_RANGE_WIDTH-1 : (r+1)*AVST_DOWN_META_W - HDR_WIDTH - PREFIX_WIDTH - BAR_RANGE_WIDTH]; + + //assign down_valid[r] = avst_down.VALID[r]; + assign down_valid[r] = avst_down.VALID[r] & down_ready; end for (genvar r = 0; r < CC_MFB_REGIONS; r++) begin @@ -139,8 +146,8 @@ module DUT ( .AVST_DOWN_EOP (avst_down.EOP), .AVST_DOWN_EMPTY (avst_down.EMPTY), .AVST_DOWN_BAR_RANGE (down_bar_range), - .AVST_DOWN_VALID (avst_down.VALID), - .AVST_DOWN_READY (avst_down.READY), + .AVST_DOWN_VALID (down_valid), + .AVST_DOWN_READY (down_ready), // ===================================================================== // Avalon-ST UP (CC+RQ) Interface - Intel FPGA Only diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/property.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/property.sv new file mode 100644 index 000000000..1cce5c45a --- /dev/null +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/property.sv @@ -0,0 +1,94 @@ +//-- properties.sv +//-- Copyright (C) 2023 CESNET z. s. p. o. +//-- Author: Radek Iša + +//-- SPDX-License-Identifier: BSD-3-Clause + +import uvm_pkg::*; +`include "uvm_macros.svh" + + +module PROPERTY #( + int unsigned RC_MFB_REGIONS, + int unsigned RC_MFB_REGION_SIZE, + int unsigned RC_MFB_BLOCK_SIZE, + int unsigned RC_MFB_ITEM_WIDTH, + int unsigned RC_MFB_META_W, + + int unsigned CQ_MFB_REGIONS, + int unsigned CQ_MFB_REGION_SIZE, + int unsigned CQ_MFB_BLOCK_SIZE, + int unsigned CQ_MFB_ITEM_WIDTH, + int unsigned CQ_MFB_META_W + +) +( + input logic RST, + // For Intel + avst_if avst_down, + avst_if avst_up, + // Credit control + crdt_if crdt_down, + crdt_if crdt_up, + // For Xilinx + axi_if cq_axi, + axi_if cc_axi, + axi_if rc_axi, + axi_if rq_axi, + // For Intel and Xilinx + mfb_if rq_mfb, + mfb_if rc_mfb, + mfb_if cq_mfb, + mfb_if cc_mfb +); + + string module_name = ""; + logic START = 1'b1; + + /////////////////// + // Start check properties after first clock + initial begin + module_name = $sformatf("%m"); + #(10ps) + START = 1'b0; + end + + //////////////////////////////////// + // RC + mfb_property #( + .REGIONS (RC_MFB_REGIONS ), + .REGION_SIZE (RC_MFB_REGION_SIZE), + .BLOCK_SIZE (RC_MFB_BLOCK_SIZE ), + .ITEM_WIDTH (RC_MFB_ITEM_WIDTH ), + .META_WIDTH (RC_MFB_META_W ) + ) + RC ( + .RESET (RST), + .vif (rc_mfb) + ); + + //////////////////////////////////// + // CQ + mfb_property #( + .REGIONS (CQ_MFB_REGIONS ), + .REGION_SIZE (CQ_MFB_REGION_SIZE), + .BLOCK_SIZE (CQ_MFB_BLOCK_SIZE ), + .ITEM_WIDTH (CQ_MFB_ITEM_WIDTH ), + .META_WIDTH (CQ_MFB_META_W ) + ) + CQ ( + .RESET (RST), + .vif (cq_mfb) + ); + + property no_fall_init; + @(posedge avst_down.CLK) disable iff(RST || START) + $rose(avst_down.READY) |=> always avst_down.READY; + endproperty + + assert property (no_fall_init) + else begin + `uvm_error(module_name, "\n\tAVST DONW interface brouke protocol. READY signal fall down after inintialization"); + end +endmodule + diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/testbench.sv b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/testbench.sv index dfe9714bf..c14f19828 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/testbench.sv +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/tbench/testbench.sv @@ -95,4 +95,38 @@ module testbench; .cc_mfb (cc_mfb) ); + + PROPERTY #( + .RC_MFB_REGIONS (RC_MFB_REGIONS ), + .RC_MFB_REGION_SIZE(RC_MFB_REGION_SIZE), + .RC_MFB_BLOCK_SIZE (RC_MFB_BLOCK_SIZE ), + .RC_MFB_ITEM_WIDTH (RC_MFB_ITEM_WIDTH ), + .RC_MFB_META_W (RC_MFB_META_W ), + + .CQ_MFB_REGIONS (CQ_MFB_REGIONS ), + .CQ_MFB_REGION_SIZE(CQ_MFB_REGION_SIZE), + .CQ_MFB_BLOCK_SIZE (CQ_MFB_BLOCK_SIZE ), + .CQ_MFB_ITEM_WIDTH (CQ_MFB_ITEM_WIDTH ), + .CQ_MFB_META_W (CQ_MFB_META_W ) + ) + PROPERTY_U ( + .RST (reset.RESET), + // For Intel + .avst_up (avst_up), + .avst_down (avst_down), + // For Credit control + .crdt_down (crdt_down), + .crdt_up (crdt_up), + // For Xilinx + .cq_axi (cq_axi), + .cc_axi (cc_axi), + .rc_axi (rc_axi), + .rq_axi (rq_axi), + // For MFB + .rq_mfb (rq_mfb), + .rc_mfb (rc_mfb), + .cq_mfb (cq_mfb), + .cc_mfb (cc_mfb) + ); + endmodule diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/top_level.fdo b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/top_level.fdo index 296f1e5a1..fec961b9b 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/top_level.fdo +++ b/core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm/top_level.fdo @@ -32,8 +32,3 @@ puts "Std Arith Warnings - Disabled" set StdArithNoWarnings 1 nb_sim_run -if {$SIM_FLAGS(CODE_COVERAGE)} { - coverage save -code bcefst -verbose actual.ucdb -} -quit -