-
Notifications
You must be signed in to change notification settings - Fork 7
/
Copy pathmax30003.c
321 lines (217 loc) · 7.9 KB
/
max30003.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include "max30003.h"
#include "max30003_define.h"
#include "nrf_gpio.h"
#include "nrf_pwr_mgmt.h"
#include "nrf_log.h"
#include "nrf_log_ctrl.h"
static nrf_drv_spi_t m_spi;
static uint8_t max30003_spi_write_buffer[4];
static uint8_t max30003_spi_read_buffer[4];
static void wait_100_ms() {
max30003_100_ms_timer = 0x00;
while (!max30003_100_ms_timer) {
if (NRF_LOG_PROCESS() == false) {
nrf_pwr_mgmt_run();
}
}
}
static void wait_100_ms_timer(uint32_t wait) {
for (uint32_t i = 0; i < wait; i++) {
wait_100_ms();
}
}
void set_max30003_spi_instance(nrf_drv_spi_t spi_instance) {
m_spi = spi_instance;
}
uint8_t max30003_spi_write(uint8_t address, uint32_t data) {
uint16_t timeout = UINT16_MAX;
memset(max30003_spi_write_buffer, 0x00, sizeof(max30003_spi_write_buffer));
memset(max30003_spi_read_buffer, 0x00, sizeof(max30003_spi_read_buffer));
max30003_spi_write_buffer[0] = (address << 1);
max30003_spi_write_buffer[1] = ((0x00FF0000 & data) >> 16);
max30003_spi_write_buffer[2] = ((0x0000FF00 & data) >> 8);
max30003_spi_write_buffer[3] = (0x000000FF & data);
spi_xfer_done = 0x00;
nrf_drv_spi_transfer(&m_spi, max30003_spi_write_buffer, 4,
max30003_spi_read_buffer, 4);
while (!spi_xfer_done && --timeout) {
}
if (!timeout) {
return 0x00;
}
return 0x01;
}
static uint8_t max30003_spi_read(uint8_t address, uint32_t *data) {
uint16_t timeout = UINT16_MAX;
memset(max30003_spi_write_buffer, 0x00, sizeof(max30003_spi_write_buffer));
memset(max30003_spi_read_buffer, 0x00, sizeof(max30003_spi_read_buffer));
max30003_spi_write_buffer[0] = (address << 1) | 1;
spi_xfer_done = 0x00;
nrf_drv_spi_transfer(&m_spi, max30003_spi_write_buffer, 4,
max30003_spi_read_buffer, 4);
while (!spi_xfer_done && --timeout) {
}
*data = 0x00;
*data |= max30003_spi_read_buffer[1] << 16;
*data |= max30003_spi_read_buffer[2] << 8;
*data |= max30003_spi_read_buffer[3];
if (!timeout) {
return 0x00;
}
return 0x01;
}
static uint8_t max30003_spi_read_ecg_sample(uint8_t address, int32_t *data) {
uint16_t timeout = UINT16_MAX;
memset(max30003_spi_write_buffer, 0x00, sizeof(max30003_spi_write_buffer));
memset(max30003_spi_read_buffer, 0x00, sizeof(max30003_spi_read_buffer));
max30003_spi_write_buffer[0] = (address << 1) | 1;
spi_xfer_done = 0x00;
nrf_drv_spi_transfer(&m_spi, max30003_spi_write_buffer, 4,
max30003_spi_read_buffer, 4);
while (!spi_xfer_done && --timeout) {
}
uint32_t data0 = (uint32_t) (max30003_spi_read_buffer[1]);
data0 = data0 << 24;
uint32_t data1 = (uint32_t) (max30003_spi_read_buffer[2]);
data1 = data1 << 16;
uint32_t data2 = (uint32_t) (max30003_spi_read_buffer[3]);
data2 = data2 >> 6;
data2 = data2 & 0x03;
uint32_t ecg = (uint32_t) (data0 | data1 | data2);
*data = (int32_t) ecg;
if (!timeout) {
return 0x00;
}
return 0x01;
}
uint8_t get_max30003_rev_id() {
max30003_info_reg max30003_info;
uint8_t spi_state = max30003_spi_read(MAX30003_INFO, &max30003_info.value);
if (spi_state) {
uint8_t id = max30003_info.bits.REV_ID;
return id;
}
return 0x00;
}
uint8_t init_max30003_mode_0() {
uint8_t spi_state = 0x01;
max30003_sw_rst_reg max30003_sw_rst;
max30003_sw_rst.value = 0x00;
max30003_spi_write(MAX30003_SW_RST, max30003_sw_rst.value);
wait_100_ms_timer(5);
max30003_cnfg_gen_reg max30003_cnfg_gen;
// max30003_cnfg_gen.value = 0x080004;
max30003_cnfg_gen.value = 0x00;
max30003_cnfg_gen.bits.EN_ECG = 1; //ECG Channel enabled
max30003_cnfg_gen.bits.RBIASN = 0; //ECGN is connected to VMID through a resistor (selected by RBIASV)
max30003_cnfg_gen.bits.RBIASP = 0; //ECGP is connected to VMID through a resistor (selected by RBIASV)
max30003_cnfg_gen.bits.RBIASV = 1;
max30003_cnfg_gen.bits.EN_RBIAS = 1;
max30003_cnfg_gen.bits.IMAG = 2;
max30003_cnfg_gen.bits.EN_DCLOFF = 1; //01 = DCLOFF Detection applied to the ECGP/N pins
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_GEN, max30003_cnfg_gen.value);
max30003_cnfg_cal_reg max30003_cnfg_cal;
// max30003_cnfg_cal.value = 0x720000;
max30003_cnfg_cal.value = 0x00;
max30003_cnfg_cal.bits.EN_VCAL = 1;
max30003_cnfg_cal.bits.VMODE = 1;
max30003_cnfg_cal.bits.VMAG = 1;
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_CAL, max30003_cnfg_cal.value);
max30003_cnfg_emux_reg max30003_cnfg_emux;
// max30003_cnfg_emux.value = 0x0B0000;
max30003_cnfg_emux.value = 0x00;
max30003_cnfg_emux.bits.CALP_SEL = 2;
max30003_cnfg_emux.bits.CALN_SEL = 3;
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_EMUX, max30003_cnfg_emux.value);
max30003_cnfg_ecg_reg max30003_cnfg_ecg;
//max30003_cnfg_ecg.value = 0x805000;
max30003_cnfg_ecg.value = 0x00;
max30003_cnfg_ecg.bits.RATE = 2;
max30003_cnfg_ecg.bits.GAIN = 3;
max30003_cnfg_ecg.bits.DHPF = 1;
max30003_cnfg_ecg.bits.DLPF = 1;
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_ECG, max30003_cnfg_ecg.value);
max30003_cnfg_rtor_reg max30003_cnfg_rtor;
//max30003_cnfg_rtor.value = 0x3FC600;
max30003_cnfg_rtor.value = 0x00;
max30003_cnfg_rtor.bits.WNDW = 3;
max30003_cnfg_rtor.bits.GAIN = 1;
max30003_cnfg_rtor.bits.EN_RTOR = 1;
max30003_cnfg_rtor.bits.PAVG = 2;
max30003_cnfg_rtor.bits.PTSF = 3;
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_RTOR1, max30003_cnfg_rtor.value);
max30003_synch_reg max30003_synch;
max30003_synch.value = 0x00;
spi_state = spi_state
& max30003_spi_write(MAX30003_SYNCH, max30003_synch.value);
return spi_state;
}
uint8_t init_max30003_mode_1() {
uint8_t spi_state = 0x01;
max30003_sw_rst_reg max30003_sw_rst;
max30003_sw_rst.value = 0x00;
spi_state = spi_state
& max30003_spi_write(MAX30003_SW_RST, max30003_sw_rst.value);
wait_100_ms_timer(5);
max30003_cnfg_gen_reg max30003_cnfg_gen;
max30003_cnfg_gen.value = 0x00;
max30003_cnfg_gen.bits.EN_ECG = 1; //ECG Channel enabled
max30003_cnfg_gen.bits.RBIASN = 1; //ECGN is connected to VMID through a resistor (selected by RBIASV)
max30003_cnfg_gen.bits.RBIASP = 1; //ECGP is connected to VMID through a resistor (selected by RBIASV)
max30003_cnfg_gen.bits.RBIASV = 1;
max30003_cnfg_gen.bits.EN_RBIAS = 1;
max30003_cnfg_gen.bits.IMAG = 2;
max30003_cnfg_gen.bits.EN_DCLOFF = 1; //01 = DCLOFF Detection applied to the ECGP/N pins
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_GEN, max30003_cnfg_gen.value);
max30003_cnfg_ecg_reg max30003_cnfg_ecg;
max30003_cnfg_ecg.value = 0x00;
max30003_cnfg_ecg.bits.RATE = 2;
max30003_cnfg_ecg.bits.GAIN = 3;
max30003_cnfg_ecg.bits.DHPF = 1;
max30003_cnfg_ecg.bits.DLPF = 1;
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_ECG, max30003_cnfg_ecg.value);
max30003_cnfg_rtor_reg max30003_cnfg_rtor;
max30003_cnfg_rtor.value = 0x00;
max30003_cnfg_rtor.bits.EN_RTOR = 1;
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_RTOR1, max30003_cnfg_rtor.value);
max30003_cnfg_emux_reg max30003_cnfg_emux;
max30003_cnfg_emux.value = 0x00;
max30003_cnfg_emux.bits.OPENN = 0;
max30003_cnfg_emux.bits.OPENP = 0;
spi_state = spi_state
& max30003_spi_write(MAX30003_CNFG_EMUX, max30003_cnfg_emux.value);
max30003_mngr_dyn_reg max30003_mngr_dyn;
max30003_mngr_dyn.value = 0x00;
max30003_mngr_dyn.bits.FAST = 0;
spi_state = spi_state
& max30003_spi_write(MAX30003_MNGR_DYN, max30003_mngr_dyn.value);
max30003_synch_reg max30003_synch;
max30003_synch.value = 0x00;
spi_state = spi_state
& max30003_spi_write(MAX30003_SYNCH, max30003_synch.value);
return spi_state;
}
uint8_t set_max30003_sync() {
max30003_synch_reg max30003_synch;
max30003_synch.value = 0x00;
return max30003_spi_write(MAX30003_SYNCH, max30003_synch.value);
}
uint8_t set_max30003_fifo_reset() {
max30003_fifo_rst_reg max30003_fifo_rst;
max30003_fifo_rst.value = 0x00;
return max30003_spi_write(MAX30003_FIFO_RST, max30003_fifo_rst.value);
}
uint8_t get_max30003_ecg_voltage_sample(int32_t *value) {
return max30003_spi_read_ecg_sample(MAX30003_ECG, value);
}